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ZL60101 TX / ZL60102 RX 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
Data Sheet
Issue 1.0 November 2002
Ordering Information ZL60101/MJD Parallel Fiber Transmitter ZL60102/MJD Parallel Fiber Receiver Options ZL6010*/MKD Module with EMI shield ZL6010*/MLD Module with external heat sink ZL6010*/MMD Module with external heat sink and EMI shield
Description Features
* * * * * * * * * * * * 12 parallel channels, total 32.6 Gbps capacity Data rate up to 2.72 Gbps per channel 850 nm VCSEL array Data I/O is CML compatible with DC blocking capacitors Link reach 300 m with 50/125 m 500 MHz.km fiber at 2.5 Gbps Channel BER better than 10-12 Industry standard MPO/MTP ribbon fiber connector interface Pluggable MegArray(R) ball grid array connector Optionally available with EMI shield and external heat sink Laser class 1M IEC 60825-1:2001 compliant Power supply 3.3 V Compatible with industry MSA The ZL60101 and ZL60102 together make a very high speed transmitter/receiver pair for parallel fiber applications. The transmitter module converts parallel electrical input signals via a laser driver and a VCSEL array into parallel optical output signals at a wavelength of 850nm. The receiver module converts parallel optical input signals via a PIN photodiode array and a transimpedance and limiting amplifier into electrical output signals. The modules are pluggable each fitted with an industrystandard MegArray(R) BGA connector. This provides ease of assembly on the host board and enables provisioning of bandwidth on demand.
Applications
* * * * * High-speed interconnects within and between switches, routers and transport equipment Proprietary backplanes Low cost SONET/SDH VSR (Very Short Reach) OC-192/STM64 connections InfiniBand(R) connections Interconnects rack-to-rack, shelf-to-shelf, boardto-board, board-to-optical backplane
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Data Sheet
ZL60101 TX / ZL60102 RX Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Transmitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Transmitter Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transmitter Control and Status Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Transmitter Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Transmitter Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Receiver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Receiver Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Receiver Control and Status Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Receiver Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Receiver Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Circuit Board Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Heading Frontplate for Panel Accessed Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Regulatory Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Eye safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electrostatic discharge immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electromagnetic interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Handling instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cleaning the optical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ESD handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Link Reach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Link Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical Interface - Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Zarlink Semiconductor Inc.
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Data Sheet Absolute Maximum Ratings
ZL60101 TX / ZL60102 RX
Not necessarily applied together. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Table 1 - Absolute Maximum Ratings Parameter Supply voltage Differential input voltage amplitude Voltage on any pin Relative humidity (non-condensing) Storage temperature ESD resistance
1. Differential input voltage amplitude is defined as V = DIN+ - DIN-. 1
Symbol VCC V VPIN MOS TSTG VESD
Min -0.3 -0.3 5 -40
Max 4.0 1.2 VCC + 0.3 95 100 1
Unit V V V % C kV
Recommended Operating Conditions
These parameters apply both to the transmitter and the receiver. Table 2 - Recommended Operating Conditions Parameter Power supply voltage Operating case temperature Signaling rate (per channel)1 Link distance2 Data I/O DC blocking capacitors3 Power supply noise4 Symbol VCC TCASE fD LD CBLK VNPS Min 3.135 0 1.0 2 100 200 Max 3.465 80 2.72 Unit V C Gbps m nF mVp-p
1. Data patterns are to have maximum run lengths and DC balance shifts no worse than that of a Pseudo Random Bit Sequence of length 223-1 (PRBS-23). Information on lower bit rates is available on request. 2. For maximum distance, see Table 19. 3. For AC-coupling, DC blocking capacitors external to the module with a minimum value of 100 nF is recommended. 4. Power supply noise is defined at the supply side of the recommended filter for all VCC supplies over the frequency range of 500 Hz to 2720 MHz with the recommended power supply filter in place.
L1 1 H
L2 6.8 nH
Host Vcc C1 10 F
R1 100
R2 1.0 k
Module Vcc
C2 10 F
C3 0.1 F
C4 0.1 F
Figure 1 - Recommended power supply filter
Zarlink Semiconductor Inc. 3
ZL60101 TX / ZL60102 RX
Transmitter Specifications
All parameters below require operating conditions according to Table 2. Table 3 - Transmitter optical and electrical specifications Parameter Optical Parameters Launch power (50/125 m MMF)1 Extinguished output power Extinction ratio2 Optical modulation amplitude3 Center wavelength Spectral width4 Relative intensity noise OMA Optical output rise time (20 - 80%) Optical output fall time (20 - 80%) Total jitter contributed (peak to Channel to channel Power dissipation Supply current Differential input voltage amplitude (peak to Differential input impedance8 Electrical input rise time (20 - 80%) Electrical input fall time (20 - 80%) peak)7 skew6 peak)5 Deterministic jitter contributed (peak to peak) Electrical Parameters PD ICC VIN ZIN tRE tFE 200 80 1.5 450 1600 120 160 160 POUT POFF ER OMA C RIN12OMA tRO tFO TJ DJ tSK 7 0.24 830 860 0.85 -116 150 150 120 50 100 -7.5 -2 -30 Symbol Min Max
Data Sheet
Unit
dBm dBm dB mW nm nmrms dB/Hz ps ps ps ps ps W mA mVp-p ps ps
1. The output optical power is compliant with IEC 60825-1 Amendment 2, Class 1M Accessible Emission Limits. 2. The extinction ratio is measured at 622 Mbps. 3. Informative. Corresponds to POUT = -7.5 dBm and ER = 7 dB. 4. Spectral width is measured as defined in EIA/TIA-455-127 Spectral Characterization of Multimode Laser Diodes. 5. Total jitter equals TP1 to TP2 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet). 6. Channel skew is defined for the condition of equal amplitude, zero ps skew signals applied to the transmitter inputs. 7. Differential input voltage is defined as the peak to peak value of the differential voltage between DIN+ and DIN-. Data inputs are CML compatible. 8. Differential input impedance is measured between DIN+ and DIN-.
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Data Sheet
ZL60101 TX / ZL60102 RX
DIN0+ DIN0-
VCSEL Driver
DIN11+ DIN11-
VCSEL Array
0 1 2 3 4 5 6 7 8 9 10 11
VCSEL Driver Controller
VCC
VEE
RESET Tx_DIS Tx_EN
FAULT
Figure 2 - Transmitter block diagram Table 4 - Transmitter optical channel assignment Front view - MTP key up Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0 Host circuit board
DIN+ 50 50 DIN-
VCC 13k 11k VEE
Figure 3 - Differential CML input equivalent circuit
Zarlink Semiconductor Inc.
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ZL60101 TX / ZL60102 RX
Transmitter Control and Status Signals
Data Sheet
The following table shows the timing relationships of the status and control signals of the pluggable optical transmitter. Table 5 - Transmitter control and status signals Parameter Control input voltage high1 Control input voltage low Control pull-up resistor Status output voltage FAULT assert time FAULT lasers off RESET duration RESET assert time RESET de-assert time Tx_EN assert time Tx_EN de-assert time Tx_DIS assert time Tx_DIS de-assert time
2 3
Symbol VIH VIL RPU1 RPD VOL RPU2 TFA TFD TTDD TOFF TON TTEN TTD TTD TTEN
Min 2.1
Typ
Max
Unit V
0.62 10 10 0.4 20 100 100 100 10 5 10 100 1 5 5 10 10 1
V k k V k s s s s ms ms s s ms
Control pull-down resistor Status pull-up resistor
4
low4, 5
1. Applies to control signals RESET, Tx_DIS and Tx_EN. 2. Applies to control signals RESET and Tx_EN. Internal pull-up resistor. 3. Applies to control signal Tx_DIS. Internal pull-down resistor. 4. Applies to status signal FAULT. Internal pull-up to VCC. 5. With status output sink current max. 2 mA.
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Data Sheet
Transmitter Control and Status Timing Diagrams
ZL60101 TX / ZL60102 RX
The following figures show the timing relationships of the status and control signals of the pluggable optical transmitter.
Vcc TTEN
Tx Output [0:11] Data [0:11]
Transmitter Not Ready
Normal operation
RESET: floating or high
Figure 4 - Transmitter power-up sequence
FAULT
TFA TFD
Data [0:11] Tx Output [0:11]
No Fault
Fault
Figure 5 - Transmitter fault signal timing diagram
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ZL60101 TX / ZL60102 RX
Data Sheet
RESET
FAULT TTDD TON
Data [0:11] Tx Output [0:11]
Transmitter Not Ready
Normal operation
Figure 6 - Transmitter reset signal timing diagram
Tx_EN TTD Data [0:11]
Tx_DIS TTD Data [0:11]
Lasers off
Lasers off
Normal operation
Tx Off
Normal operation
Tx Off
Tx_EN TTEN
Data [0:11]
Transmitter Not Ready
Normal operation
Figure 7 - Transmitter enable and disable timing diagram Table 6 - Truth table for transmitter operation (Pre-condition: RESET floating or HIGH) Tx_DIS High Tx_EN High Tx_EN Low Transmitter disabled Transmitter disabled Tx_DIS Low Normal operation Transmitter disabled
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Zarlink Semiconductor Inc.
Data Sheet
Transmitter Pinout Assignments
ZL60101 TX / ZL60102 RX
Table 7 - Transmitter host circuit board layout (Top view, toward MPO/MTP connector end) K 1 2 3 4 5 6 7 8 9 10
NIC NIC NIC NIC NIC NIC NIC DNC DNC DNC
J
NIC NIC VCC VCC VCC VCC NIC RESET Tx_EN DNC
H
NIC NIC VCC VCC VCC VCC NIC FAULT Tx_DIS DNC
G
VEE VEE VEE DIN3+ DIN3VEE DIN0+ DIN0VEE DNC
F
VEE VEE DIN4+ DIN4VEE DIN1+ DIN1VEE VEE DNC
E
VEE DIN5+ DIN5VEE DIN2+ DIN2VEE VEE VEE DNC
D
VEE VEE VEE DIN6+ DIN6VEE DIN11DIN11+ VEE DNC
C
VEE VEE DIN7+ DIN7VEE DIN10DIN10+ VEE VEE DNC
B
VEE DIN8+ DIN8VEE DIN9DIN9+ VEE VEE VEE DNC
A
NIC VEE VEE NIC VEE VEE NIC NIC NIC DNC
(10x10 array, 1.27 mm pitch) Transmitter Pin Description Table 8 - Transmitter pin descriptions Signal Name DIN[0:11] +/VCC VEE Type Data input Description Transmitter data in, channel 0 to 11 Transmitter power supply rail Transmitter signal common. All transmitter voltages are referenced to this potential unless otherwise stated. Control input Control input Status output Transmitter enable. HIGH: normal operation LOW: disable transmitter Transmitter disable. HIGH: disable transmitter LOW: normal operation Transmitter fault. HIGH: normal operation LOW: laser fault detected on at least one channel Transmitter reset. HIGH: normal operation LOW:reset to clear fault signal Do not connect to any potential, including ground. No internal connection. Directly connect these pads to the PC board transmitter signal ground plane. Comments Internal differential termination at 100 .
Tx_EN
Active high, internal pull-up. See Table 6. Active high, internal pull-down. See Table 6. When active, all channels are disabled. Clear by reset signal. Internal pull-up.
Tx_DIS
FAULT
RESET
Control input
Internal pull-up.
DNC NIC
Zarlink Semiconductor Inc.
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ZL60101 TX / ZL60102 RX
Receiver Specifications
Data Sheet
All parameters below require operating conditions according to Table 2 and a termination load of 100 differential at the electrical output. Table 9 - Receiver optical and electrical parameters Parameter Optical Parameters Input optical power Center wavelength Return loss
2 1
Symbol
Min
Max
Unit
PIN C RL peak)3 TJ DJ PSS tSK PSA PSD PD ICC peak)6 VOUT ZL PSE tRE tFE
10-12
-16 830 12
-2 860 120 50 -11.3 100 -17
dBm nm dB ps ps dBm ps dBm dBm
Total jitter contributed (peak to Stressed receiver sensitivity Channel to channel Signal detect assert Signal detect de-assert skew5
4
Deterministic jitter contributed (peak to peak)
-27 1.5 450 500 80 0.3 150 150 800 120
Electrical Parameters Power dissipation Supply current Differential output voltage amplitude (peak to Output differential load Stressed receiver eye impedance7 opening8 W mA mVp-p UI ps ps
Electrical output rise time (20 - 80 %) Electrical output fall time (20 - 80 %)
1. Receive power for a channel is measured for a BER of and worst case extinction ratio. PIN (Min) is measured using a fast rise/fall time source with low RIN and adjacent channel(s) operating with with incident power of 6 dB above PIN (Min). 2. Return loss is measured as defined in TIA/EIA-455-107A Determination of Component Reflectance or Link/System Return Loss Using a Loss Test Set. 3. Total jitter equals TP3 to TP4 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet). 4. The stressed receiver sensitivity is measured using PRBS 223-1 pattern, 2.7 dB inter-symbol interference, ISI (Min), 30 ps duty cycle dependent deterministic jitter, DCD DJ (Min), and 7 dB extinction ratio, ER (Min) (ER penalty = 1.76 dB). All channels not under test are receiving signals with an average input power of 6 dB above PIN (Min). 5. Channel skew is defined for the condition of equal amplitude, zero ps skew signals applied to the receiver inputs. 6. Differential output voltage is defined as the peak to peak value of the differential voltage between DOUT+ and DOUT- and measured with a 100 differential load connected between DOUT+ and DOUT-. Data outputs are CML compatible. 7. See Figure 19. 8. The stressed receiver eye opening represents the eye at TP4 as defined in IEEE 802.3 clauses 38.2 and 38.6 (Gigabit Ethernet). The stressed receiver eye opening is measured using PRBS 223-1 pattern, 2.7 dB ISI min, 30 ps DCD DJ min, 7 dB ER min and an average input power of -10.8 dBm (0.5 dB above minimum stressed receiver sensitivity as defined in IEEE 802.3 clause 38.6). All channels not under test are receiving signals with an average input power of 6 dB above PIN (Min).
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Data Sheet
ZL60101 TX / ZL60102 RX
0 1 2 3 4 5 6 7 8 9 10 11
PIN Array
TransImpedance and Limiting Amplifier
DOUT0+ DOUT0-
DOUT11+ DOUT11-
VCC VEE
Rx_EN Rx_SD SQ_EN
Figure 8 - Receiver block diagram Table 10 - Receiver optical channel assignment Front view - MTP key up Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0 Host circuit board
Receiver Control and Status Signals The following table shows the timing relationships of the status and control signals of the pluggable optical receiver. Table 11 - Receiver control and status signals Parameter Control input voltage high1 Control input voltage Control input pull-up Status output pull-up low1 current1
2, 3
Symbol VIH VIL IIN VOL RPU TSD TLOS TRXEN TRXD
Min 2.0
Typ
Max
Unit V
0.9 10 3.25 50 50 33 5 200 200 100 0.4
V A V k s s ms s
Status output voltage low
resistor2
Receiver signal detect assert time Receiver signal detect de-assert time Receiver enable assert time Receiver enable de-assert time
1. Applies to control signals Rx_EN, SQ_EN. 2. Applies to status signal Rx_SD. Internal pull-up to VCC. 3. With status output sink current max 2 mA.
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ZL60101 TX / ZL60102 RX
Receiver Control and Status Timing Diagrams
Data Sheet
The following figures show the timing relationships of the status and control signals of the pluggable optical receiver.
Rx_EN TRXD
ICC
Normal Operation
Rx Off
Figure 9 - Receiver enable signal timing diagram
Rx_SD TLOS Signal No Signal
Figure 10 - Receiver signal detect timing diagram
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Data Sheet
Receiver Pinout Assignments
ZL60101 TX / ZL60102 RX
Table 12 - Receiver pinout assignments (Top view, toward MPO/MTP connector end) K 1 2 3 4 5 6 7 8 9 10
DNC DNC NIC NIC NIC NIC NIC DNC DNC SQ_EN
J
NIC NIC VCC VCC VCC VCC NIC NIC Rx_EN DNC
H
NIC NIC VCC VCC VCC VCC Rx_SD NIC NIC DNC
G
VEE VEE VEE DOUT3DOUT3+ VEE DOUT0DOUT0+ VEE DNC
F
VEE VEE DOUT4DOUT4+ VEE DOUT1DOUT1+ VEE VEE DNC
E
VEE DOUT5DOUT5+ VEE DOUT2DOUT2+ VEE VEE VEE DNC
D
VEE VEE VEE DOUT6DOUT6+ VEE DOUT11+ DOUT11VEE DNC
C
VEE VEE DOUT7DOUT7+ VEE DOUT10+ DOUT10VEE VEE DNC
B
VEE DOUT8DOUT8+ VEE DOUT9+ DOUT9VEE VEE VEE DNC
A
NIC VEE VEE NIC VEE VEE NIC NIC NIC DNC
(10x10 array, 1.27 mm pitch)
Receiver Pin Description Table 13 - Receiver pin descriptions Signal Name DOUT[0:11] +/VCC VEE Type Data output Description Receiver data out, channel 0 to 11. Receiver power supply rail. Receiver signal common. All receiver voltages are referenced to this potential unless otherwise stated. Control input Status output Control input Receiver enable. HIGH: normal operation LOW: disable receiver Receiver signal detect. HIGH: valid optical input on all channels LOW: loss of signal on at least one channel Squelch enable. HIGH: squelch function enabled. Data OUT is squelched on any channels that have loss of signal LOW: squelch function disabled Do not connect to any potential, including ground. No internal connection. Directly connect these pads to the PC board transmitter signal ground plane. Internal pull-up. Comments
Rx_EN
Rx_SD
Internal pull-up.
SQ_EN
Internal pull-up.
DNC NIC
Zarlink Semiconductor Inc.
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ZL60101 TX / ZL60102 RX
Package Outline
Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters.
Data Sheet
Figure 11 - Module layout (MJD option)
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Zarlink Semiconductor Inc.
Data Sheet
ZL60101 TX / ZL60102 RX
Table 14 - Module dimensions (MJD option) Key A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 S1 T1 U1 V1 W1 X1 Y1 Dimension [mm] 36.87 17.50 14.40 4.30 12.23 7.48 12.50 3.26 0.98 0.76 31.75 30.23 13.72 1.145 19.43 O3.63 2-56 UNC-2B 16.89 O1.30 O2.50 7.55 27.64 Comments Length of module body, less optical receptacle assembly Width of module body Width of optical receptacle assembly Height of bottom of optical receptacle assembly Height of top of optical receptacle assembly Length of optical receptacle assembly Height of top of module Clearance over host board at rear of module Height of standoff boss on front posts Height of front posts Distance from rear post to front plane, less optical receptacle assembly Distance from front to rear posts Distance between posts, side to side Location of BGA pin A1 Location of BGA pin A1, transmitter Diameter of rear posts Thread dimension, minimum 3.50 mm deep Location of BGA pin A1, receiver Diameter of front posts Diameter of standoff boss on front post Height of back of module without heat sink Length of external heat sink body
Dimensions with reference designators ending in "2" (e.g., C2) are defined in Table 17.
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ZL60101 TX / ZL60102 RX
Data Sheet
Figure 12 - Module layout with EMI shield (MKD option) Table 15 - Module dimensions with EMI shield (MKD option) Key Dimension [mm] Min AA1 AB1 AC1 9.10 15.50 8.27 11.10 17.50 Max Distance from hostboard to centre of EMI shield Height of EMI shield with bezel in A2 location Width of EMI shield with bezel in A2 location Comments
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Data Sheet
ZL60101 TX / ZL60102 RX
Figure 13 - Module layout with external heat sink (MLD option) Table 16 - Module dimensions with external heat sink (MLD option) Key Z1 AD1 AE1 Dimension [mm] 15.19 24.00 17.45 Comments Height of top of module, including external heat sink Length of external heat sink Width of external heat sink
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ZL60101 TX / ZL60102 RX
Circuit Board Footprint Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters.
Data Sheet
Figure 14 - Host circuit board footprint layout Table 17 - Host circuit board footprint dimensions Key A2 B2 C2 D2 E2 F2 G2 Dimension [mm] 35.31 5.15 O0.58 O4.50 O2.69 O1.70 O3.30 Tolerance [mm] 0.75 0.25 0.05 MIN 0.12 0.12 MIN Comments Distance from rear post to inside surface of bezel Distance from rear post to rear of module keep-out area Diameter of pad in BGA pattern Diameter of keep-out pad for rear posts: two rear and one front Diameter of hole for mounting screws: two rear and one front Diameter of hole for front posts Diameter of keep-out pad for front post
Dimensions with reference designators ending in "1" (e.g., B1, C1) are defined in Table 14.
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Data Sheet
Heading Frontplate for Panel Accessed Modules Tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters.
ZL60101 TX / ZL60102 RX
Figure 15 - Host frontplate layout Table 18 - Host frontplate dimensions Key A3 B3 C3 D3 E3 Dimension [mm] 18.42 16.50 0.50 3.20 13.33 Tolerance [mm] MIN 0.20 MAX 0.20 0.20 Comments Centre-to-centre spacing for adjacent modules Width of opening in frontplate Corner radius of opening in frontplate Height from host PCB to bottom of frontplate opening Height from host PCB to top of frontplate opening
Dimensions with reference designators ending in "2" (e.g., A2) are defined in Table 17.
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ZL60101 TX / ZL60102 RX
Thermal Characteristics
There are three options for heat sinks depending on the cooling needs. They are 1. Direct application without any attached external heat sink 2. Use the generic heat sink specified in this data sheet 3. Use a customer designed external heat sink
Data Sheet
In Figure 16 and Figure 17, the temperature rise and thermal resistance as a function of air velocity (free air velocity at the top of the module) is shown for option 1 and 2. The thermal resistance is defined as the temperature difference between the case temperature and ambient flowing air divided by the total heat dissipation of the module. Improved thermal properties can be achieved by using a larger heat sink especially if more height is available (option 3). For this option, a more detailed discussion with Zarlink is recommended regarding heat sink design attachment materials.
Temperature rise at 1.5W (Free stream air velocity)
20 16 12
Option ZL6010*/ML
Temperature rise (K)
8 4 0 0 1 2 Air velocity (m/s) 3 4
Option ZL6010*/MJ
Figure 16 - Temperature difference between ambient flowing air and case at a heat dissipation of 1.5 W
Thermal resistance to air (Free stream air velocity)
15
Thermal resistance (K/W)
10
Option ZL6010*/ML
5
Option ZL6010*/MJ
0 0 1 2 Air velocity (m/s) 3 4
Figure 17 - Thermal resistance, as a function of air velocity (the airflow is along the shortest side of the module). For any other orientation, the thermal resistance is 75-100% of the values shown above
20
Zarlink Semiconductor Inc.
Data Sheet Regulatory Compliance
Eye safety
ZL60101 TX / ZL60102 RX
The maximum optical output power is specified to comply with Class 1M in accordance with IEC 60825-1:2001. In addition the transmitter complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice No.50, dated July 26, 2001. No maintenance or service of the product may be performed. Electrostatic discharge The module is classified as Class 1 (> 1000 Volts) according to MIL-STD-883, test method 3015.7, with regards to the electrical pads. Electrostatic discharge immunity The part withstand a 15 kV (air discharge) and 8 kV (contact discharge) either indirect or directly to receptacle; tested according to IEC 61000-4-2, while in operation without addition of bit errors. Electromagnetic interference Emission The electromagnetic emission is tested in front of the module (module fitted with EMI shield), with the module mounted in a frontplate cutout as defined in Figure 15. The part is tested with FCC Part 15, 30 - 1000 MHz and 1 GHz to 5th harmonic of the highest fundamental frequency (6.75 GHz), and is specified to be Class B with > 6 dB margin. Immunity The electromagnetic immunity is tested without a front panel or enclosure. The module specification is maintained with an applied field of 10 V/m for frequencies between 10 kHz and 10 GHz, according to IEC 61000-4-3 and GR-1089-CORE.
Handling instructions
Cleaning the optical interface A protective connector plug is supplied with each module. This plug should remain in place prior to use, and be reattached whenever a fiber cable is not inserted. This will keep the optical interface free from dust or other contaminants, which may potentially degrade the optical signal. Before reattaching the connector plug to the module, visually inspect the plug and remove any contamination. If the optical interface becomes contaminated, it can be cleaned with high-pressure nitrogen. The use of fluids, or physical contact with the optical interface, is not advised due to potential for damage. ESD handling When handling the modules, precautions for ESD sensitive devices should be taken. These include use of ESD protected work areas with wrist straps, controlled work-benches, floors etc.
Zarlink Semiconductor Inc.
21
ZL60101 TX / ZL60102 RX
Link Reach
Data Sheet
The following table lists the minimum reach distance of the 12 channel pluggable optical modules for different multimode fiber (MMF) types and bandwidths assuming worst case parameters. Each case allows for a maximum of 2 dB per channel connection loss for patch cables and other connectors. Table 19 - Link reach for different fiber types and data rates Fiber Type [core / cladding m] 62.5/125 MMF 62.5/125 or 50/125 MMF 50/125 MMF Modal Bandwidth @ 850 nm [MHz*km] 200 400 500 Reach Distance @ 1 Gbps [m] 350 650 750 Reach Distance @ 2.5 Gbps [m] 130 260 300 Reach Distance @ 2.72 Gbps [m] 110 220 270
Link Model Parameters The link reaches above have been calculated using the following link model parameters and Gigabit Ethernet link model version 2.3.5 (filename: 5pmd047.xls). Table 20 - Link model parameters Parameter Mode partition noise k-factor Modal noise Dispersion slope parameter Wavelength of zero dispersion Attenuation coefficient at 850 nm Conversion factor Q-factor [BER 10-12] TP4 eye opening DCD allocation at TP3 RMS baseline wander S.D. RIN coefficient Conversion factor DCD DJ BLW kRIN c_rx Symbol k MN SO UO dB C1 Q Value 0.3 0.3 0.11 1320 3.5 480 7.04 0.3 0.08 0.025 0.70 329 ns.MHz UI UI dB ps/nm2*km nm dB/km ns.MHz Unit
22
Zarlink Semiconductor Inc.
Data Sheet Electrical Interface - Application Examples
ZL60101 TX / ZL60102 RX
Recommended CML output
Transmitter CML input
Host PCB
100nF ZOUT=100 Differential Z0=100 Differential 100nF ZIN=100 Differential
Figure 18 - Recommended differential CML input interface
Receiver CML output
Recommended CML input
Host PCB
100nF Z0=100 Differential 100nF ZTERM =100 Differential
ZL
Figure 19 - Recommended differential CML output interface
Zarlink Semiconductor Inc.
23
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Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved.
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